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 8051 instruction set

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PostSubject: 8051 instruction set   Tue Jul 31, 2007 7:12 pm

The instruction set is divided in to 5 categories. They are as follows:

1. Arithmetic instructions.
2. Logic instructions.
3. Data transfer instructions.
4. Boolean variable manipulation instruction.
5. Program and machine control instruction













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PostSubject: .   Tue Jul 31, 2007 7:14 pm

Acall targetaddress


Function : Absolute call

Flags : None

Description: ACALL unconditionally calls a subroutine located at the indicated address. The instruction increments the PC twice to obtain the address of the following instruction, then pushes the 16-bit result onto the stack (low-order byte first) and increments the stack pointer twice. The destination address is obtained by successively concatenating the five high-order bits of the incremented PC, op code bits 7-5, and the second byte of the instruction.



The subroutine called must therefore start within the same 2K block of program memory as the first byte of the instruction following ACALL. No flags are affected.

Example: Initially SP equals 07H. The label "SUBRTN" is at program memory location 0345H. After executing the instruction ACALL SUBRTN at location 0123H, SP will contain 09H, internal RAM location 08H and 09H will contain 25H and 01H, respectively, and the PC will contain 0345H.

Operation: ACALL

(PC) ← (PC) + 2

(SP) ← (SP) + 1

((SP)) ← (PC7-0)

(SP) ← (SP) + 1

((SP)) ←(PC15-Cool

(PC10-0) ← page address

Bytes: 2

Cycles: 2


ADD A, sourse byte

Function : Add

Flags : OV, AC, CY

Description: ADD adds the byte variable indicated to the accumulator, leaving the result in the accumulator. The carry and auxiliary carry flags are set, respectively, if there is a carry out of bit 7 or bit 3, and cleared otherwise. When adding unsigned integers, the carry flag indicates an overflow occurred. OV is set if there is a carry out of bit 6 but not out of bit 7, or a carry out of bit 7 but not out of bit 6; otherwise OV is cleared. When adding signed integers, OV indicates a negative number produced as the sum of two positive operands, or a positive sum from two negative operands. Four source operand addressing modes are allowed: register, direct, register indirect, or immediate.

Example: mov A,#45H ; A = 45H
add A,#4FH

Result: A = 94H, CY = 0.



The following addressing modes are supported for the ADD instruction.
1. Immediate: ADD A, #data

Example: ADD A,#40H

2. Register: ADD A, Rn

Example: ADD A,R1

3. Direct: ADD A, direct

Example: ADD A, 20H ;Add data in RAM location 20H to A

4. Register-indirect: ADD A,@Ri

Example: ADD A,@R0 ;Add to A data pointed by R0


ADDC A, source byte

Function : Add with carry

Flags : OV, AC, CY

Description: ADDC simultaneously adds the byte variable indicated, the carry flag and the accumulator contents, leaving the result in the accumulator. The carry and auxiliary carry flags are set, respectively, if there is a carry out of bit 7 or bit 3, and cleared otherwise. When adding unsigned integers, the carry flag indicates an overflow occurred.

OV is set if there is a carry out of bit 6 but not out of bit 7, or a carry out of bit 7 but not out of bit 6; otherwise OV is cleared. When adding signed integers, OV indicates a negative number produced as the sum of two positive operands or a positive sum from two negative operands.

Four source operand addressing modes are allowed: register, direct, register indirect, or immediate.

Example: mov a, #0C3H ; (A) ← 0C3H
mov R0,#0AAH ; (R0) ← 0AAH assume (CY) = 1
ADDC A, R0

Result : (A) = 6EH with (AC) = 0, (CY) = 1, (OV) = 1.

The addressing modes for ADDC are same as for ADD A,byte.



AJMP target address

Function : Absolute jump

Flags : None

Description: AJMP transfers program execution to the indicated address, which is formed at runtime by concatenating the high-order five bits of the PC (after incrementing the PC twice), op code bits 7-5, and the second byte of the instruction. The destination must therefore be within the same 2K block of program memory as the first byte of the instruction following AJMP.

Example: The label ”JMPADR” is at program memory location 0123H. The instruction AJMP JMPADR is at location 0345H and will load the PC with 0123H.



ANL dest-byte, src-byte

Function : Logical AND for byte variables

Flags : None

Description: ANL performs the bitwise logical AND operation between the variables indicated and stores the results in the destination variable. No flags are affected. The two operands allow six addressing mode combinations. When the destination is a accumulator, the source can use register, direct, register-indirect, or immediate addressing; when the destination is a direct address, the source can be the accumulator or immediate data.

Note: When this instruction is used to modify an output port, the value used as the original port data will be read from the output data latch, not the input pins.

Example: If the accumulator holds 0C3H (11000011B) and register 0 holds 0AAH(10101010B) then the instruction ANL A,R0 will leave 81H (10000001B) in the accumulator.



For an ANL instruction there are a total of six addressing modes.

1. Immediate: ANL A, #data

Eample : ANL A,#30h

2. Register: ANL A, Rn

Example : ANL A, R5

3. Direct: ANL A,direct

Example : ANL A,20H ; AND A with data in RAM location 20H

4. Register-indirect: ANL A, @Ri

Example : ANL A,@R1 ; AND A with data pointed by R0



In the next two addressing modes the destination is direct address while the source is either A or immediate data.



5. ANL direct,A

Example : ANL 20H, A

6. ANL direct, #data

Example : ANL 40H, #30H



ANL C, src-bit

Function : Logical AND for bit variables

Flags : CY

Description: In this instruction the carry flag bit is ANDed with a source bit and the result is placed in carry. If the Boolean value of the source bit is a logic 0 then clear the carry flag; otherwise leave the carry flag in its current state. Only direct bit addressing is allowed for the source operand. A slash (”/”) preceding the operand in the assembly language indicates that the logical complement of the addressed bit is used as the source value, but the source bit itself is not affected.
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PostSubject: ..   Tue Jul 31, 2007 7:15 pm

CJNE dest-byte, src-byte, target

Function : Compare and jump if not equal

Flags : CY

Description: CJNE compares the magnitudes of the first two operands, and branches if their values are not equal. The branch destination is computed by adding the signed relative displacement in the last instruction byte to the PC, after incrementing the PC to the start of the next instruction. The carry flag is set if the unsigned integer value of dest-byte is less than the unsigned integer value of src-byte; otherwise, the carry is cleared. Neither operand is affected.















The first two operands allow four addressing mode combinations: the accumulator may be compared with any directly addressed byte or immediate data, and any indirect RAM location or working register can be compared with an immediate constant.

1. Immediate: CJNE A, #data, target

Example: CJNE A, #40, GO ; JUMP if A is not 40

2. Direct: CJNE A, direct, target

Example: CJNE A, 20H, GO ; JUMP if A !=(20H)

3. Register: CJNE Rn,#data,target

Example: CJNE R5,#70,GO ;jump if R5 is not 70

In the fourth addressing mode, any RAM location can be destination. The RAM location is held by register R0 or R1.

4. Register-indirect: CJNE @Ri,#data,target

Example: CJNE @R1,#40,GO ;Jump if RAM location whose address is held by R1 is not equal to 40.



CLR A

Function: Clear accumulator

Flags: None are affected

Description: The accumulator is cleared (all bits set to zero).

Example: The accumulator contains 5CH. The instruction CLR A will leave the accumulator set to 00H



CLR bit

Function: Clear bit

Flags: None are affected

Description: The indicated bit is cleared (reset to zero). CLR can operate on the carry flag or any directly addressable bit.

Example: Port 1 has previously been written with 5DH (01011101B). The instruction CLR P1.2 will leave the port set to 59H (01011001B).



CPL A

Function: Complement accumulator

Flags: None are affected

Description: Each bit of the accumulator is logically complemented (one’s complement). Bits which previously contained a one are changed to zero and vice versa.

Example: The accumulator contains 5CH (01011100B). The instruction CPL A will leave the accumulator set to 0A3H (10100011 B).



CPL bit

Function: Complement bit

Flags: None are affected

Description: The bit variable specified is complemented. A bit which had been a one is changed to zero and vice versa. CPL can operate on the carry or any directly addressable bit.

Example: Port 1 has previously been written with 5DH (01011101B).

The instruction sequence

CPL P1.1

CPL P1.2

will leave the port set to 5BH (01011011B).



DA A

Function: Decimal adjust accumulator after addition

Flags: CY

Description: DA A adjusts the eight-bit value in the accumulator resulting from the earlier addition of two variables (each in packed BCD format), producing two four-bit digits. Any ADD or ADDC instruction may have been used to perform the addition. If accumulator bits 3-0 are greater than nine (1010-1111), or if the AC flag is one, six is added to the accumulator producing the proper BCD digit in the low order nibble. This internal addition would set the carry flag if a carry-out of the low order four-bit field propagated through all high-order bits, but it would not clear the carry flag otherwise. If the carry flag is now set, or if the four high-order bits now exceed nine (1010-1111), these high-order bits are incremented by six, producing the proper BCD digit in the high-order nibble. Again, this would set the carry flag if there was a carryout of the high-order bits, but wouldn’t clear the carry. The carry flag thus indicates if the sum of the original two BCD variables is greater than 100, allowing multiple precision decimal addition. OV is not affected. All of this occurs during the one instruction cycle. Essentially; this instruction performs the decimal conversion by adding 00H, 06H, 60H, or 66H to the accumulator, depending on initial accumulator and PSW conditions.

Note: DA A cannot simply convert a hexadecimal number in the accumulator to BCD notation, nor does DA A apply to decimal subtraction.

Example: MOV A, #47H
ADD A, #38H
DA A

Result: 47H
+ 38H
-----------
7FH (invalid BCD)
06H (after DA A)
-----------
85H (valid BCD)
-----------

In the above instruction, since the lower nibble was greater than 9, DA added 6 to A. If the lower nibble is less than 9 but AC=1, it also adds 6 to the lower nibble.



DEC byte

Function: Decrement

Flags: None

Description: The variable indicated is decremented by 1. An original value of 00H will underflow

to 0FFH. Four operand addressing modes are allowed:

1. Accumulator: DEC A

2. Register: DEC Rn

3. Direct: DEC direct

4. Register-indirect: DEC @Ri



DIV AB

Function: Divide

Flags: CY and OV

Description: DIV AB divides the unsigned eight-bit integer in the accumulator by the unsigned eight-bit integer in register B. The accumulator receives the integer part of the quotient; register B receives the integer remainder. The carry and OV flags will be cleared.

Exception: If B had originally contained 00H, the values returned in the accumulator and B register will be undefined and the overflow flag will be set. The carry flag is cleared in any case.

Example: MOV A,#35
MOV B,#10
DIV AB

Result: A=3 and B=5



DJNZ byte, target

Function: Decrement and jump if not zero

Flags: None

Description: DJNZ decrements the location indicated by 1, and branches to the address indicated by the second operand if the resulting value is not zero. An original value of 00H will underflow to 0FFH. The branch destination would be computed by adding the signed relative-displacement value in the last instruction byte to the PC, after incrementing the PC to the first byte of the following instruction.

The following two formats are supported by this instruction.

1. Register: DJNZ Rn, target

Example: DJNZ R3, HERE

2. Direct: DJNZ direct, target
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PostSubject: Re: 8051 instruction set   Tue Jul 31, 2007 7:15 pm

INC byte

Function: Increment

Flgs: None

Description: INC increments the indicated variable by 1. An original value of 0FFH will overflow to 00H.

Four operand addressing modes are allowed:

1. Accumulator: INC A

2. Register: INC Rn

3. Direct: INC direct

4. Register-indirect: INC @Ri















Note: When this instruction is used to modify an output port, the value used as the original port data will be read from the output data latch, not the input pins.


INC DPTR

Function: Increment data pointer

Flags: None

Description: Increment the 16-bit data pointer by 1. A 16-bit increment (modulo 216) is performed; an overflow of the low-order byte of the data pointer (DPL) from 0FFH to 00H will increment the high- order byte (DPH). This is the only 16-bit register which can be incremented.

Example: MOV DPTR, #16FFH DPTR=16FFH
INC DPTR

Result: DPTR=1700H


JB bit, target

Function: Jump if bit is set

Flags: None

Description: If the indicated bit is a one, jump to the target address indicated; otherwise proceed with the next instruction. The branch destination is computed by adding the signed relative-displacement in the third instruction byte to the PC, after incrementing the PC to the first byte of the next instruction. The bit tested is not modified.

Example:
SETB P1.2 ; Make P1.2 an input port
HERE: JB P1.2,HERE ; stay here as long as P1.2=1
MOV P2,#20H ; Since P1.2=0 send 55H to P2



JBC bit, target

Function: Jump if bit is set and clear bit

flags: None

Description: If the indicated bit is one, branch to the target address while at the same time clear the designated bit. The branch destination is computed by adding the signed relative displacement in the third instruction byte to the PC, after incrementing the PC to the first byte of the next instruction.

Note: When this instruction is used to test an output pin, the value used as the original data will be read from the output data latch, not the input pin.



JC target

Function: Jump if carry is set

Flags: None

Description: If the carry flag is set, branch to the target address indicated; otherwise proceed with the next instruction.


JMP @A + DPTR

Function: Jump indirect
Flags: None

Description: The JMP instruction is an unconditional jump to a target address. The target address provided by the total sum of register A and the DPTR register.



JNB bit, target

Function: Jump if bit is not set

Flags: None

Description: If the indicated bit is a zero, branch to the target address; otherwise proceed with the next instruction. The branch destination is computed by adding the signed relative-displacement in the third instruction byte to the PC, after incrementing the PC to the first byte of the next instruction. The bit tested is not modified.

Example:
SETB P1.2 ; Make P1.2 an input port
HERE: JNB P1.2,HERE ; stay here as long as P1.2=0
MOV P2,#20H ; Since P1.2=1 send 55H to P2


JNC target

Function: Jump if carry is not set

Flags: None

Description: If the carry flag is a zero, branch to the target address ; otherwise proceed with the next instruction. The branch destination is computed by adding the signed relative-displacement in the second instruction byte to the PC, after incrementing the PC twice to point to the next instruction. The carry flag is not modified.


JNZ target

Function: Jump if accumulator is not zero
Flags; None

Description: If any bit of the accumulator is a one, branch to the indicated address; otherwise proceed with the next instruction. The branch destination is computed by adding the signed relative-displacement in the second instruction byte to the PC, after incrementing the PC twice. The accumulator is not modified.


JZ target

Function: Jump if accumulator is zero

Flags: None

Description: If all bits of the accumulator are zero, branch to the address indicated; otherwise proceed with the next instruction. The branch destination is computed by adding the signed relative-displacement in the second instruction byte to the PC, after incrementing the PC twice. The accumulator is not modified. No flags are affected.



LCALL 16-bit addr

Function: Long call

Flags: None

Description: LCALL calls a subroutine located at the indicated address. The instruction adds three to the program counter to generate the address of the next instruction and then pushes the 16-bit result onto the stack (low byte first), incrementing the stack pointer by two. The high-order and low-order bytes of the PC are then loaded, respectively, with the second and third bytes of the LCALL instruction. Program execution continues with the instruction at this address. The subroutine may therefore begin anywhere in the full 64 Kbyte program memory address space.

Example: Initially the stack pointer equals 07H. The label ”SUBRTN” is assigned to program memory location 1234H. After executing the instruction LCALL SUBRTN at location 0123H, the stack pointer will contain 09H, internal RAM locations 08H and 09H will contain 26H and 01H, and the PC will contain 1234H.


LJMP 16-bit addr

Function: Long jump

Flags: None

Description: LJMP causes an unconditional branch to the indicated address, by loading the high order and low-order bytes of the PC (respectively) with the second and third instruction bytes. The destination may therefore be anywhere in the full 64K program memory address space.

Example: The label ”JMPADR” is assigned to the instruction at program memory location 1234H. The instruction LJMP JMPADR at location 0123H will load the program counter with 1234H.
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PostSubject: Re: 8051 instruction set   Tue Jul 31, 2007 7:16 pm

MOV dest-byte, src-byte

Function: Move byte variable

Flags: None

Description: The byte variable indicated by the second operand is copied into the location specified by the first operand. The source byte is not affected. No other register or flag is affected.

There are fifteen possible combinations for this instruction. They are as follows:















(a) Register A as the destination. This can have the following formats.

1. MOV A, #data Example: MOV A,#10H
2. MOV A, Rn Example: MOV A,R5
3. MOV A, direct Example: MOV A,50H
4. MOV A, @Ri Example: MOV A,@R0

(b) Register A is the source. This can have the following formats.

1. MoV Rn, A
2. MOV direct, A
3. MOV @Ri, A

(c) Rn is the destination

1. MOV Rn, #immediate
2. MOV Rn, A
3. MOV Rn, direct

(d) The destination direct address

1. MOV direct, #data
2. MOV direct, @ri
3. MOV direct, A
4. MOV direct, Rn

(e) Destination is an indirect address held by R0 and R1.

1. MOV @Ri, #data
2. MOV @Ri, A
3. MOV @Ri, direct



MOV dest-bit, src-bit

Function: Move bit data

Flags: None

Description: The Boolean variable indicated by the second operand is copied into the location specified by the first operand. One of the operands must be the carry flag; the other may be any directly addressable bit. No other register or flag is affected.

Example: MOV P1.2,C ;copy carry bit to port bit P1.2



MOV DPTR, #data16

Function: Load data pointer with a 16-bit constant

Flags: None

Description: The data pointer is loaded with the 16-bit constant indicated. The 16 bit constant is loaded into the second and third bytes of the instruction. The second byte (DPH) is the high-order byte, while the third byte (DPL) holds the low-order byte. This is the only instruction which moves 16 bits of data at once.

Example: MOV DPTR, #434FH ;DPTR=434FH



MOVC A, @A + base-reg

Function: Move code byte

Flags: None

Description: The MOVC instructions load the accumulator with a code byte, or constant from program memory. The address of the byte fetched is the sum of the original unsigned eight-bit accumulator contents and the contents of a sixteen-bit base register, which may be either the data pointer or the PC. In the latter case, the PC is incremented to the address of the following instruction before being added to the accumulator; otherwise the base register is not altered. Sixteen-bit addition is performed so a carry-out from the low-order eight bits may propagate through higher-order bits.

Example: MOVC A, @A + DPTR ;mov data at A+DPTR into A

MOVC A, @A + PC ;mov data at A+PC into A



MOVX dest-byte, src-byte

Function: Move external

Flags: None

Description: The MOVX instructions transfer data between the accumulator and a byte of external data memory, hence the ”X” appended to MOV. This instruction allows us to access externally connected memory. There are two types of instructions, differing in whether they provide an eight bit or sixteen-bit indirect address to the external data RAM as explained bellow.

(a) The 16-bit external memory address is held by the DPTR register.

MOVX A,@DPTR

This moves into the accumulator a byte from external memory whose address is pointed by DPTR.

MOVX @DPTR, A

This moves the content of accumulator to the external memory location whose address is held by DPTR.

(b) The 8-bit address of external memory is held by R0 or R1

MOVX A,@Ri

This moves to the accumulator a byte from external memory whose 8-bit address is pointed by R0 or R1.

MOVX @Ri,A

This moves a byte from register A to an external memory whose 8-bit address is held by R0 or R1.



MUL AB

Function: Multiply

Flags: OV, CY

Description: MUL AB multiplies the unsigned eight-bit integers in the accumulator and register B. The low-order byte of the sixteen-bit product is left in the accumulator, and the high-order byte in B. If the product is greater than 255 (0FFH) the overflow flag is set; otherwise it is cleared. The carry flag is always cleared.

Example: MOV A,#5
MOV B,#7
MUL AB

Result: A=35=23H, B=0



NOP

Function: No operation

Flags: None

This performs no operation and execution continues with the next instruction. It is sometimes used for timing delays to waste clock cycles. This instruction only updates the PC to point to the next instruction following NOP.


ORL dest-byte, src-byte

Function: Logical OR for byte variables

Flags: None

Description: ORL performs the bitwise logical OR operation between the indicated variables, storing the results in the destination byte.

The two operands allow six addressing mode combinations. When the destination is the accumulator, the source can use register, direct, register-indirect, or immediate addressing; when the destination is a direct address, the source can be the accumulator or immediate data.

Note: When this instruction is used to modify an output port, the value used as the original port data will be read from the output data latch, not the input pins.

Example: If the accumulator holds 0C3H (11000011B) and R0 holds 55H (01010101B) then the instruction ORL A,R0 will leave the accumulator holding the value 0D7H (11010111B).

Different types of addressing modes are as follows.

1. Immediate: ORL A, #data

Eample : ORL A,#30h

2. Register: ORL A, Rn

Example : ORL A, R5

3. Direct: ORL A,direct

Example : ORL A,20H ; OR A with data in RAM location 20H

4. Register-indirect: ORL A, @Ri

Example : ORL A,@R1 ; OR A with data pointed by R0



ORL C, src-bit

Function: Logical OR for bit variables

Flags: CY

Description: In this instruction the carry flag bit is ANDed with a source bit and the result is placed in carry. If the Boolean value of the source bit is a logic 0 then clear the carry flag; otherwise leave the carry flag in its current state. Only direct bit addressing is allowed for the source operand. A slash (”/”) preceding the operand in the assembly language indicates that the logical complement of the addressed bit is used as the source value, but the source bit itself is not affected. No other flags are affected.


POP direct

Function: Pop from stack

Flags: None

Description: This copies the byte pointed by SP to the location whose direct address indicated, and decrements SP by 1. Notice that this instruction supports only direct addressing mode. Therefore, instruction such as POP A, POP R3 is illegal.

Example: POP 0E0H Where E0H is the RAM address belonging to Register A.

Operation:
(direct) ← ((SP))

(SP) ← (SP) – 1



PUSH direct

Function: Push onto stack

Flags: None

Description: This copies the indicated byte onto the stack increments SP by 1. Notice that this instruction supports only direct addressing mode. Therefore, instruction such as PUSH A, PUSH R3 is illegal.

Example: PUSH 0E0H Where E0H is the RAM address belonging to Register A.

Operation:

(SP) ← (SP) + 1

((SP)) ← (direct)
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PostSubject: Re: 8051 instruction set   Tue Jul 31, 2007 7:17 pm

RET

Function: Return from subroutine

Flags: None

Description: This instruction is used to return from a subroutine. RET pops the high and low-order bytes of the PC successively from the stack, decrementing the stack pointer by two. Program execution continues at the resulting address, generally the instruction immediately following an ACALL or LCALL.















RETI

Function: Return from interrupt

Flags: None

Description: This instruction is used to return from an interrupt service routine. RETI pops the high and low-order bytes of the PC successively from the stack, and restores the interrupt logic to accept additional interrupts at the same priority level as the one just processed. The stack pointer is left decremented by two. The PSW is not automatically restored to its pre-interrupt status. Program execution continues at the resulting address, which is generally the instruction immediately after the point at which the interrupt request was detected. If a lower or same-level interrupt is pending when the RETI instruction is executed, that one instruction will be executed before the pending interrupt is processed.


RL A

Function: Rotate accumulator left

Flags: None

Description: The eight bits in the accumulator are rotated one bit to the left. Bit 7 is rotated into the bit 0 position.

Example: The accumulator holds the value 0C5H (11000101B). The instruction RL A leaves the accumulator holding the value 8BH (10001011B) with the carry unaffected.


RLC A

Function: Rotate accumulator left through carry flag

Flags: CY

Description: The eight bits in the accumulator and the carry flag are together rotated one bit to the left. Bit 7 moves into the carry flag; the original state of the carry flag moves into the bit 0 position.

Example: The accumulator holds the value 0C5H (11000101B), and the carry is zero. The instruction

RLC A leaves the accumulator holding the value 8AH (10001010B) with the carry set.


RR A

Function: Rotate accumulator right

Flags: None

Description: The eight bits in the accumulator are rotated one bit to the right. Bit 0 is rotated into the bit 7 position.

Example: The accumulator holds the value 0C5H (11000101B). The instruction RR A leaves the accumulator holding the value 0E2H (11100010B) with the carry unaffected.


RRC A

Function: Rotate accumulator right through carry flag

Flags: CY

Description: The eight bits in the accumulator and the carry flag are together rotated one bit to the right. Bit 0 moves into the carry flag; the original value of the carry flag moves into the bit 7 position.

Example: The accumulator holds the value 0C5H (11000101B), the carry is zero. The instruction

RRC A leaves the accumulator holding the value 62H (01100010B) with the carry set.


SETB bit

Function: Set bit

Description: SETB sets the indicated bit to one. SETB can operate on the carry flag or any

directiy addressable bit of a port, register, or RAM location.

Example: SETB P1.2
SETB ACC.2
SETB C ;carry flag CY=1


SJMP target

Function: Short jump

Flags: None

Description: Program control branches unconditionally to the address indicated. The branch destination is computed by adding the signed displacement in the second instruction byte to the PC, after incrementing the PC twice. Therefore, the range of destinations allowed is from 128 bytes preceding this instruction to 127 bytes following it.

Example: The label ”RELADR” is assigned to an instruction at program memory location 0123H. The instruction SJMP RELADR will assemble into location 0100H. After the instruction is executed, the PC will contain the value 0123H.


SUBB A, src-byte

Function: Subtract with borrow

Flags: OV, AC, CY

Description: SUBB subtracts the src-byte and the carry flag together from the accumulator, leaving the result in the accumulator. The steps for subtraction perform by the internal hardware of the CPU are as follows:

1. Take 2's complement of the src-byte.
2. Add this to register A.
3. Invert the carry.

This instruction sets the carry flag according to the following.

CY

If dest>source 0 The result is positive
If dest=source 0 The result is 0
If dest<source 1 The result is negative in 2's compliment


Different types of addressing modes are as follows.

1. Immediate: SUBB A, #data

Eample : SUBB A,#30h ; A = A - 30H - CY

2. Register: SUBB A, Rn

Example : SUBB A, R5 ; A = A - R5 - CY

3. Direct: SUBB A,direct

Example : SUBB A,20H ; A - data at (20H) - CY

4. Register-indirect: SUBB A, @Ri

Example : SUBB A,@R1 ; A - data at (R1) - CY


SWAP A

Function: Swap nibbles within the accumulator

Flags: None

Description: SWAP A interchanges the low and high-order nibbles (four-bit fields) of the accumulator (bits 3-0 and bits 7-4). The operation can also be thought of as a four bit rotate instruction.

Example: MOV A, #25H
SWAP A

Result: A = 52H


XCH A, byte

Function: Exchange accumulator with byte variable

Flags: None

Description: This instruction swaps the content of register A and the source byte. The source byte can be any register or RAM location.

Example: MOV A, #49H ; A = 49H
MOV R2, #30H ; R2 = 30H
XCH A,R2

Result: A=30H, R2=49H

Different types of addressing modes are as follows.

1. Register: XCH A, Rn

Example : XCH A, R5

2. Direct: XCH A, direct

Example : XCH A, 20H

3. Register-indirect: XCH A, @Ri

Example : XCH A,@R1


XCHD A,@Ri

Function: Exchange digit

Flags: None

Description: XCHD exchanges the low-order nibble of the accumulator (bits 3-0), with that of the internal RAM location indirectly addressed by the specified register. The high-order nibbles (bits 7-4) of each register are not affected.

Example: R0 contains the address 20H. The accumulator holds the value 36H. Internal RAM location 20H holds the value 75H. The instruction XCHD A, @ R0 will leave RAM location 20H holding the value 76H and 35H in the accumulator.


XRL dest-byte, src-byte

Function: Logical Exclusive OR for byte variables

Flags: None

Description: XRL performs the bitwise logical Exclusive OR operation between the indicated variables, storing the results in the destination.

Example: MOV A, #28H
XRL A, #08H

Result: A = 20H

For XRL instruction there are total of 6 addressing modes. In four of them the accumulator must be the destination. They are as follows:

1. Immediate: XRL A, #data

Eample : XRL A,#30h

2. Register: XRL A, Rn

Example : XRL A, R5

3. Direct: XRL A,direct

Example : XRL A,20H ; XOR A with data in RAM location 20H

4. Register-indirect: XRL A, @Ri

Example : XRL A,@R1 ; XOR A with data pointed by R0

In the next two addressing modes the destination is direct address while the source is either A or immediate data.

5. XRL direct,A

Example : XRL 20H, A

6. XRL direct, #data

Example : XRL 40H, #30H
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PostSubject: Re: 8051 instruction set   Today at 11:48 am

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8051 instruction set
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